Compute performance demand has been growing exponentially in recent years, and with the advent of Generative AI, this demand is growing even faster. Moore’s law coming to an end as well as the Memory Wall (bandwidth & capacity) are the main performance bottlenecks. The chiplet system-in-package (SiP) is the industry's solution to these bottlenecks. Silicon interposers are industry’s main technology to connect chiplets in SiPs, but they introduce several new bottlenecks. The largest interposer going to production is 2700mm2, which is ~1/4 the largest standard package substrate. Thus, a SiP with silicon interposer has limited compute & memory chiplets, thus limited performance.
This presentation introduces Universal Memory Interface (UMI), a high bandwidth efficient D2D connectivity technology between compute and memory chiplets. UMI PHY on standard packaging provides similar bandwidth/power to D2D PHYs with silicon interposers, thus enables creation of large & powerful SiPs required to address Gen AI applications.

Shell Upstream has been processing large subsurface datasets for multiple decades driving significant business value.  Many of the state of the art algorithms for this have been developed using deep domain knowledge and have benefitted from the hardware technology improvements over the years. However, the demand for more efficient processing as datasets get bigger and the algorithms become even more complex is ever-growing. This talk will focus on the memory and data management challenges for a variety of traditional HPC workflows in the energy industry. It will also cover unique challenges for accelerating modern AI-based workflows requiring new innovations. 

There are a set of challenges that emanate from memory issues in GenAI deployments in enterprise
• Poor tooling for performance issues related from GPU and memory interconnectedness
• Latency issues as a result of data movement and poor memory capacity planning
• Failing AI training scenarios in low memory constraints

There is both opacity and immature tooling to manage a foundational infrastructure for GenAI deployment, memory. This is experienced by AI teams who need to double-click on the infrastructure and improve on these foundations to deploy AI at scale.

As the cost of sequencing drops and the quantity of data produced by sequencing grows, the amount of processing dedicated to genomics is increasing at a rapid pace.  [Genomics is evolving in a number of directions simultaneously.]  Complex pipelines are written in such a manner that they are portable to either clusters or clouds.  Key kernels are also being ported to GPUs in a drop-in replacement for their non-accelerated counterpart.  These techniques are helping to address challenges of scaling up genomics computations and porting validated pipelines to new systems.  However, all of these computations strain the bandwidth and capacity of available resources.  In this talk, Roche´s Tom Sheffler will share an overview of the memory-bound challenges present in genomics and venture some possible solutions.

What does an Intellectual Property strategy mean?  Most IP professionals consider an IP strategy to be setting goals, targets, and priorities, but have you considered framing your concepts for achieving your IP targets and expectations? This discussion emphasizes moving away from last-minute actions and adopting mid- and long-term approaches to ultimately contribute significantly to company results. By showing you how to build a solid alignment of IP activities with business objectives, we aim to provide you with the knowledge to create an “IP Ecosystem,” which will drive operational excellence in a sustainable way.